Top "Vhdl" questions

Does VHDL have a ternary operator?

I love the neatness of the ternary operator vs if clauses. Does this operator exist in vhdl? My search was …

vhdl ternary-operator

VCD dump for vhdl simulation via modelsim. HOWTO?

It's the first time i try to generate a VCD and i am getting some troubles. I have a testbench …

simulation dump vhdl modelsim

VHDL: The following files are missing: .stx, .ncd, .xrpt

Before I even start with synthesis(as soon as I press "Save"), I get this warnings: WARNING:ProjectMgmt - File …

file save warnings vhdl synthesis

VHDL: is using inout port bad practise?

I have a program where i'm using inout port following way: port : inout unsigned(9 downto 0); ... if port > 10 then port &…

port vhdl

Ideas for a flexible/generic decoder in VHDL

I want to create an address Decoder that is flexible enough for me to use when changing the number of …

vhdl fpga xilinx

Type vs Subtype and down vs to for Integers in VHDL

What is the difference between type and subtype in VHDL and where should I use them ? My understanding is that …

vhdl

VHDL - type declaration in package

I am trying to scroll a text on the 7 segment display. The text will be entered from a keyboard and …

text vhdl shift segment

VHDL/Verilog related programming forums?

Hardware design with VHDL or Verilog is more like programming nowadays. However, I see SO members are not so actively …

vhdl verilog system-verilog systemc

Creating a VHDL backend for LLVM?

LLVM is very modular and allows you to fairly easily define new backends. However most of the documentation/tutorials on …

llvm vhdl

how do i initialize a std_logic_vector in VHDL?

i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below: architecture Behavioral of test …

vhdl hdl xilinx-ise