Top "Modelsim" questions

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC.

What is the difference between Verilog ! and ~?

So it ended up that the bug that had kept me on for days, was a section of code that …

verilog boolean-logic modelsim
Debugging Iteration Limit error in VHDL Modelsim

I'm writing VHDL code for a d-flip-flop on Modelsim and I get an error when I try to simulate it: …

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Power function in vhdl

I want to make power function using vhdl where the power is floating number and the number is integer (will …

vhdl modelsim
How does signal assignment work in a process?

I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this …

vhdl modelsim
How to open Modelsim project files

I can open Modelsim project files by doing File->Recent Projects. However I do not know any other way …

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ModelSim-Altera error

I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to …

linux licensing modelsim intel-fpga quartus
Why ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0?

Why does Modelsim complain about the component instantiation i1? Time: 0 ps Iteration: 1 Instance: /vhdl2_uppgift_1_extra_vhd_tst/i1 ** Warning: …

vhdl modelsim
Changing the modelsim.ini file (ModelSim)

I would like to make a modifications on several parameters in ModelSim like the MessageFormat for instance. To that extent, …

default-value modelsim
Reset modelsim editor to the default one

I want to reset my editor to the default one in Modelsim but I don't know how. When I double …

editor vhdl modelsim
How to generate a detail report of functional coverage in Questasim?

How to generate the detailed coverage report of functional coverage? I am using following command to simulate my code : vlog …

code-coverage modelsim questasim function-coverage