Debugging Iteration Limit error in VHDL Modelsim

vhdl modelsim
user607444 picture user607444 · Feb 14, 2012 · Viewed 34.8k times · Source

I'm writing VHDL code for a d-flip-flop on Modelsim and I get an error when I try to simulate it:

Error: (vsim-3601) Iteration limit reached at time 400 ps.

I'm not sure what it means, but I've looked through much of my source code for errors to no success. Can anyone guess what the problem might be?

Answer

Ahmed Soliman picture Ahmed Soliman · May 13, 2013

This error usually indicates that ModelSim is stuck in an infinite loop. In VHDL, this can happen when a signal is placed in the sensitivity list and this signal is changed in the process. The signal changes, triggering the process, which changes the signal, which again triggers the process and the cycle continues.

The following is a simple example of a process that causes an infinite loop:

PROCESS (count)

BEGIN

count <= not count;

END PROCESS;

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