What is the difference between Verilog ! and ~?

verilog boolean-logic modelsim
SleepingSpider picture SleepingSpider · May 7, 2013 · Viewed 43.8k times · Source

So it ended up that the bug that had kept me on for days, was a section of code that should have evaluated to False evaluating to True. My initial code went something like:

if(~x && ~y) begin
    //do stuff
end

i.e. If x is NOT ONE and y is NOT ONE then do stuff. Stepping through the debugger, I realized even though x was 1 the expression in the if-statement still resulted into TRUE and the subsequent code was executed.

However, when I changed the statement to: 

if(x == 0 && y == 0) begin
//do stuff
end

and also tried: 

if(!x && !y) begin
//do stuff
end

the code within the if-statement was not evaluated which was the expected behaviour. I understand that ~ is a bitwise negation and ! a logical negation, but shouldn't (~x && ~y) and (!x && !y) evaluate to the same thing? I'm afraid the codebase is too large, so I can't paste it here, but this was the only alteration I made to make the code to work as I intended. Thanks.

In response, to one of the comments below, I have created a test-case to test this behaviour:

`timescale 10ns/1ns

module test_negation();
        integer x, y;

    initial begin
        x = 1; y = 0;

        if(~x && ~y) begin
            $display("%s", "First case executed");
        end

        if(!x && !y) begin
            $display("%s", "Second case executed");
        end

        if(x == 0 && y == 0) begin
            $display("%s", "Third case executed");
        end
    end endmodule

And strangely enough, "First case executed" is printed to confirm the original behaviour I observed.

Answer

SleepingSpider picture SleepingSpider · May 7, 2013

I see. The variable "x" in the above code was a Verilog integer (integer x;). However, an integer variable is represented by Verilog as a 32-bit integer number. So even though x was "1" as I had observed, ~x will not result in "0" but in "11111111111111111111111111111110"! And so it's no surprise that the First Case was executed. My fault. Thanks for all the answers.

Related questions

How to declare and use 1D and 2D byte arrays in Verilog?

How to declare and use 1D and 2D byte arrays in Verilog? eg. how to do something like byte a_2D[3][3]; byte a_1D[3]; // using 1D for (int i=0; i< 3; i++) { a_1D[i] = (byte)i; } // using 2D for (…

Read More
Verilog: How to instantiate a module

If I have a Verilog module 'top' and a verilog module 'subcomponent' how do I instantiate subcomponent in top? top: module top( input clk, input rst_n, input enable, input [9:0] data_rx_1, input [9:0] data_rx_2, output [9:0] data_tx_2 ); subcomponent: module …

Read More
Using wire or reg with input or output in Verilog

When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?

Read More