Top "Modelsim" questions

display a real in verilog but bitstoreal returning only 0.000000

I am trying to display a real number during the simulation of my verilog code in modelsim. But I only …

verilog modelsim

Global declarations are illegal in Verilog 2001 syntax!

I have written something small in verilog: `define LW 6'b100011 `define SW 6'b101011 parameter [3:0] i_fetch = 4'b0001, decode_rr = 4'b0010, …

syntax global verilog modelsim

How to concatenate strings with integer in report statement?

I'm having trouble getting the following report statement to work: report "ERROR: instruction address '" & CONV_INTEGER(a(7 downto 2)) &…

vhdl modelsim intel-fpga quartus