I have written something small in verilog:
`define LW 6'b100011
`define SW 6'b101011
parameter [3:0]
i_fetch = 4'b0001,
decode_rr = 4'b0010,
mem_addr = 4'b0100,
alu_exec = 4'b1000;
and i am getting this error: Error: test.v(5): (vlog-2155) Global declarations are illegal in Verilog 2001 syntax.
What I am doing wrong? I am using ModelSim XE III/Starter 6.4b - Custom Xilinx Version!
Your parameter
statement has to be within a module:
module a_module ();
parameter a_parameter = 4;
endmodule
In fact, most stuff in verilog has to be within a module block.