Top "Intel-fpga" questions

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined

I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also …

vhdl intel-fpga quartus
VHDL assigning literals

I'm trying to use unsigned integers in VHDL with well defined bit widths. It seems VHDL does not like me …

vhdl unsigned-integer intel-fpga
Conversion from numeric_std unsigned to std_logic_vector in vhdl

I have a question related to conversion from numeric_std to std_logic_vector. I am using moving average filter …

vhdl fpga xilinx hdl intel-fpga
How to assign pins in Quartus II

We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have …

vhdl intel-fpga quartus
Programming VHDL on Linux?

Anyone knows good environment to program VHDL and simulate it (don't matter Xilinx or Altera) using Linux?

linux vhdl xilinx intel-fpga
VHDL - Incrementing Register Value on Push Button Event

I am very new to VHDL and am trying to figure out how to do something fairly basic on an …

vhdl fpga intel-fpga
ModelSim-Altera error

I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to …

linux licensing modelsim intel-fpga quartus
4 bit adder in vhdl

im pretty new to the vhdl language so please bear with me. I just did the vhdl code for a 1 …

vhdl intel-fpga
Trying to blink LED in Verilog

I have a CPLD with a 50Mhz clock. This is my code: module FirstProject(clk, LED); output LED; input clk; …

verilog timing intel-fpga
How to generate .rbf files in Altera Quartus?

What are .rbf files and how can i generate them from the Quartus output file .sof on windows ?

fpga intel-fpga quartus