How to assign pins in Quartus II
We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we'd use Altera this time around so I am trying to get used to Quartus II.
In particular, I am looking for a way to explicityly assign pins to the chip I am using. In Xilinx, I'd edit the netlist file but I can find no such thing in Quartus. There is a program (Assignments => Pin Planner) that does this, but it has a clunky GUI and I'd far prefer to edit the pins in a text editor, so my twofold question is
A: How do I find the file that stores the pin assignment? It's not listed under my files in the project navigator but the pins I've assigned in Pin Planner stay from session to session so they must be stored somewhere.
B: Is this a horrible idea?
IDE is Quartus II 10.1 Development kit is MAX II Development Board Language is VHDL
EDIT: Right now, I've run into the problem that I'm trying to interface with the Dev Kit through USB. I'm making a serial data receiver on it and have given it a Data In pin. The Dev Kit has a USB receiver so I'm trying to map din to whichever pin the USB connector is on. According to a file I have (rm_maxII-develop_board-rev1.pdf) the USB connector is on "Board Designation U13" but when I go into the Pin PLanner and try to assign that, there is no PIN_U13. I suspect this is an error in the pdf, rather than in Pin Planner but seing as I've never worked with Altera products before, I'm very confused.
Answer
A) You need to edit the *.qsf file, and add lines similar to the following:
set_location_assignment PIN_AP30 -to qdr_q[35]
B) While I will sometimes use the pin planner in the early stages of a design, I almost exclusively edit the qsf file directly when modifying pins, adding or removing VHDL files from the design, etc. To be completely safe, when making large changes (particularly to optimization or compiler settings) I will make sure Quartus is not running. I've been working this way with Quartus since it came out, and have not had any problems.
Once your design is compiled, you can refer to the *.pin file to see the final pinout for the FPGA. In particular, refer to the column indicating whether or not the pin is manually assigned, as any pins not specifically assigned to a location will change pretty much every time you recompile the chip (which is sub-optimal if you've already made a PCB! :).