VHDL assigning literals

vhdl unsigned-integer intel-fpga
Christopher Brown picture Christopher Brown · Mar 18, 2014 · Viewed 32k times · Source

I'm trying to use unsigned integers in VHDL with well defined bit widths. It seems VHDL does not like me trying to assign literal values to these types defined as:

variable LCD_DATA: unsigned(19 downto 0) := 0;

But in my IDE (Quartus), I get a complaint "UNSIGNED type does not match integer literal." I also get complaints for adding numbers to types defined like this. Whats the preferred change I need to make?

Answer

fru1tbat picture fru1tbat · Mar 18, 2014

See other answers, and note that for non-zero literals, you probably want to do something like:

variable LCD_DATA: unsigned(19 downto 0) := to_unsigned(n, 20);

Substitute a literal for n. This works for n=0 too, of course, but it's not as tidy as (others => '0').

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