Concatenating bits in VHDL

concatenation vhdl
Zain Rizvi picture Zain Rizvi · Oct 16, 2008 · Viewed 144.6k times · Source

How do you concatenate bits in VHDL? I'm trying to use the following code:

Case b0 & b1 & b2 & b3 is ...

and it throws an error

Thanks

Answer

user21246 picture user21246 · Oct 16, 2008

The concatenation operator '&' is allowed on the right side of the signal assignment operator '<=', only

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