ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC.
As you can see, the font of modelsim's text editor is very small. But I can't change the size in …
linux fedora modelsimSome background: I am writing a VHDL test bench for a ethernet MAC. The testbench consists of a package and …
io vhdl modelsimBelow is the code that I am running. My question is why doesn't the 3rd wait until trigger in modelsim? …
vhdl fpga modelsimIs there a way to tell the simulator (I'm using Modelsim) to pull a signal to weak 'H' when it's …
vhdl modelsim___Hi, everyone. I have instantiated a PLL using the Megawizard in Quartus II. Then I wanted to simulate it using …
vhdl fpga modelsimIt's the first time i try to generate a VCD and i am getting some troubles. I have a testbench …
simulation dump vhdl modelsimI need to get the values of several signals to check them against the simulation (the simulation is in Matlab). …
vhdl modelsimI am running some VHDL through ModelSim. Each error and warning has its own error code (like this: (vcom-1292) Slice …
vhdl fpga modelsimI am trying to run a test simulation in ModelSim and am getting the error in the title. I have …
verilog system-verilog modelsim