How can I read binary data in VHDL/modelsim whithout using special binary formats

Question

Some background:

I am writing a VHDL test bench for a ethernet MAC. The testbench consists of a package and an combined entity + architecture file. I want to read the ethernet frames that the testbench will send to the MAC from a binary file which I exported from wireshark.
I'm writing in VHDL 2008 and I'm using a Mentor Graphics Model Technology ModelSim ALTERA vcom 10.0d Compiler.

The Problem:

All solutions for reading binary data in VHDL/modelsim that I've found so far use special file formats where 1 bit of the bit_vector is represented by several bits in the file. I would like VHDL to read the binary file into 8 bit bit_vectors.
Closest I've gotten so far was using a character type file, where I can write 8 bit ASCII characters directly in binary representation.

Answer 1

I've found the solution. If I want to interpret the data directly in 8 bit parts I need to use a file of the type character and convert them to integers using the 'POS attribute. I can then convert these integers to bit vectors. This is how I did it:

LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_bit.ALL;

LIBRARY std;
  USE std.textio.all;

...

TYPE t_char_file IF FILE OF character;
TYPE t_byte_arr IS ARRAY (natural RANGE <>) OF bit_vector(7 DOWNTO 0);

SIGNAL read_arr_byte : t_byte_arr(0 to 199);

...

read_file: PROCESS (start) IS
  FILE file_in : t_char_file OPEN read_mode IS "./38478.bin";  -- open the frame file for reading
  VARIABLE char_buffer : character;
BEGIN
  IF start'EVENT AND start = '1' THEN
    FOR i IN read_arr_byte'RANGE LOOP
      read(file_in, char_buffer);
      read_arr_byte(i) <= bit_vector(to_unsigned(character'POS(char_buffer), 8));
    END LOOP;  -- i
    file_close(file_in);
  END IF;
END PROCESS read_file;