Weak 'H', Pullup on inout bidirectional signal in simulation

vhdl modelsim
Russell picture Russell · Oct 1, 2013 · Viewed 10k times · Source

Is there a way to tell the simulator (I'm using Modelsim) to pull a signal to weak 'H' when it's not being driven by either bidirectional interface?

For example if I have an I2C signal I2C_SDA that is declared as an inout from 2 modules. One is my actual UUT and the other is a testbench. Both have statements like this:

io_i2c_sda <= r_I2C_DATA when r_I2C_DATA_EN = '1' else 'Z';

So both ends are tri-stated. This works fine in simulation, except that the line is BLUE ('Z') all the time that neither end is transmitting. How can I pull-up this line to a 'H' in the code when neither end is transmitting?

Answer

Yann Vernier picture Yann Vernier · Oct 1, 2013

For VHDL, it should be possible to simply add an extra driver to the signal (which has to be of std_logic type), with the constant value 'H'. In Verilog one would use a simple '1' driver and the net type wand for wired and. 'H' specifically means a weak high driver, so it will be overridden by the low drivers.

Related questions

Debugging Iteration Limit error in VHDL Modelsim

I'm writing VHDL code for a d-flip-flop on Modelsim and I get an error when I try to simulate it: Error: (vsim-3601) Iteration limit reached at time 400 ps. I'm not sure what it means, but I've looked through much of …

Read More
Power function in vhdl

I want to make power function using vhdl where the power is floating number and the number is integer (will be always "2"). 2^ some floating number. I use ieee library and (fixed_float_types.all, fixed_pkg.all, and float_pkg.…

Read More
How does signal assignment work in a process?

I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this example here: ... signal x,y,z : bit; ... process (y) begin x<=y; z<=not x; end process; The …

Read More