Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs
How to generate the detailed coverage report of functional coverage? I am using following command to simulate my code : vlog …
code-coverage modelsim questasim function-coverageclass conf; typedef struct packed { int ns_size; int limit; } ns; int num_ns_supported; ns num_ns[]; function new(…
system-verilog function-coverage questasim