Top "Vhdl" questions

Implementing a FSM in VHDL

Just wondering if I'm implementing a finite state machine in VHDL whether or not I need to state what all …

vhdl fsm

VHDL - Incrementing Register Value on Push Button Event

I am very new to VHDL and am trying to figure out how to do something fairly basic on an …

vhdl fpga intel-fpga

When to use VHDL library std_logic_unsigned and numeric_std?

I use VHDL-200X in ISE.I always use data type like std_logic_vector,std_logic,integer,boolean and …

vhdl fpga

How to set up Eclipse for FPGA design in VHDL and Verilog)?

I am new with Eclipse, I have used it for SW development and in Altra environment for Nios processor. But …

eclipse eclipse-plugin vhdl verilog fpga

4 bit adder in vhdl

im pretty new to the vhdl language so please bear with me. I just did the vhdl code for a 1 …

vhdl intel-fpga

Why ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0?

Why does Modelsim complain about the component instantiation i1? Time: 0 ps Iteration: 1 Instance: /vhdl2_uppgift_1_extra_vhd_tst/i1 ** Warning: …

vhdl modelsim

When should I use std_logic_vector and when should I use other data types?

I'm new to VHDL and am having trouble figuring out which data types are appropriate to use where. If I …

integer port vhdl unsigned signed

How to make the 2-complement of a number without using adder

In two-complement to invert the sign of a number you usually just negate every bit and add 1. For example: 011 (3) 100 + 1 = 101 (-3) …

vhdl verilog fpga twos-complement

Difference between unsigned and std_logic_vector

can anyone tell me about the difference between below written statement. signal A: **unsigned**(3 downto 0); signal B: **std_logic_vector**(3 …

vhdl fpga

Generate random values in VHDL function

I have a design were I'm writing/reading to/from a RAM and perform some computation on the read values. …

vhdl uniform