When should I use std_logic_vector and when should I use other data types?

integer port vhdl unsigned signed
Emil Eriksson picture Emil Eriksson · May 27, 2011 · Viewed 14.6k times · Source

I'm new to VHDL and am having trouble figuring out which data types are appropriate to use where. If I understand correctly, for synthesis, all top level entity ports should be declared either std_logic_vector or std_logic and never any other type.

But std_logic_vector doesn't support arithmetics so how should I handle this?

My intuition tells me that I should simply use std_logic_vector at the top level and then convert this to and from integral data types when passing it to other entities. Is this correct?

And what integral data type (integer, unsigned, signed) should be used where? I understand the difference between signed and unsigned but when should I use integer?

Answer

Jan Decaluwe picture Jan Decaluwe · May 27, 2011

Use the data types that are most appropriate for your modeling purposes, including for ports. It is simply not true that synthesis requires that you should only use std_logic or std_logic_vector for ports. Don't believe those that tell you otherwise.

If you need bit vectors with arithmetic support, consider signed/unsigned from ieee.numeric_std. (In VHDL 2008, there is a standard package that adds arithmetic support to std_logic_vector, but I consider that evil.)

There may only be an issue at the very top-level after synthesis, when you want to simulate the synthesized net list. The port types of that net list may not match your top-level RTL interface. However, you can easily fix that when instantiating the gate level, by doing the proper conversions at that moment. That is the proper time for such low-level concerns - they should not influence your RTL modeling style.

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