Top "Vhdl" questions

VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?

Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented (…

integer logic width vhdl synthesis

Error in VHDL (Xilinx): failed to link the design

why I get error in VHDL for this? Also, sometimes: cannot do process as a process failed previously? Many thanks.

vhdl xilinx

Integer to real conversion function

Is there a common conversion function to convert a integer type object to a real type in VHDL? This is …

type-conversion vhdl real-datatype

Power function in vhdl

I want to make power function using vhdl where the power is floating number and the number is integer (will …

vhdl modelsim

How does signal assignment work in a process?

I learned that a signal is not changed immediately when encountering an expression, but when the process ends. In this …

vhdl modelsim

ONE clock period pulse based on trigger signal

i am making a midi interface. UART works fine, it sends the 8 bit message along with a flag to a …

triggers vhdl clock pulse

padding out std_logic_vector with leading zeros

ok, what I would like to do is assign a smaller std_vector to a large one, padding out the …

vhdl

How to represent Integer greater than integer'high

Is there any way to use pre-defined types from STD_LOGIC_1164 or STD_NUMERIC to represent an integer ranging from 0 …

vhdl

VHDL: Is there a convenient way to assign ascii values to std_logic_vector?

In verilog, I can assign a string to a vector like: wire [39:0] hello; assign hello = "hello"; In VHDL, I'm having …

ascii vhdl verilog

Structural 4 bit ring counter with D flip flop. VHDL / GHDL

I don't know how to do this with structural programming... "A binary counter (with reset signal) of 4 bits made of 4 …

vhdl counter ghdl