Top "Vhdl" questions

Bitwise ANDING Of Two STD_LOGIC_VECTORS

Hey I was wondering if it was at all possible in VHDL to AND two STD_LOGIC_VECTORS together. For …

controller vhdl vga

VHDL: use the length of an integer generic to determine number of select lines

I'm trying to create a reusable barrel shifter; it takes an input array of bits and shifts them a certain …

generics vhdl

VHDL initialize vector (the length is not a multiple of 4) in hex

For example, I have a vector which length is 10. How can I initialize it in hex. (The synthesize tool complains …

initialization vhdl stdvector

What to use for VHDL/digital-logic simulation on Mac OS X

I suddenly realized that there is no Altera Quartus or Xilins ISE or ModelSim on Mac OS X. What do …

macos simulation vhdl digital-logic

Professional VHDL IDE?

Is there a good IDE to work with VHDL projects ? Or are most of the professionals working with emacs/vim/…

ide vhdl

Reverse bit order on VHDL

I'm having trouble doing something like b(0 to 7) <= a(7 downto 0) when I compile it with ghdl, I have an …

vhdl

What to_unsigned does?

Could someone please explain me how VHDL's to_unsigned works or confirm that my understanding is correct? For example: C(30 …

type-conversion vhdl unsigned twos-complement signed-integer

Assign a single bit from STD_LOGIC_VECTOR to STD_LOGIC

It seems like I have done this plenty of times, but for some reason today it just doesn't want to …

vhdl

Confusion between Behavioural and Dataflow model Programs in VHDL

I'm using the textbook "VHDL: Programming By Example" by Douglas L Perry, Fourth Edition. He gave an example of the …

vhdl dataflow

Debugging Iteration Limit error in VHDL Modelsim

I'm writing VHDL code for a d-flip-flop on Modelsim and I get an error when I try to simulate it: …

vhdl modelsim