Assign a single bit from STD_LOGIC_VECTOR to STD_LOGIC

vhdl
krb686 picture krb686 · Mar 28, 2014 · Viewed 35.9k times · Source

It seems like I have done this plenty of times, but for some reason today it just doesn't want to work.

I would like to assign the MSB of a 16-bit vector to a single-bit variable.

Din : in  STD_LOGIC_VECTOR (15 downto 0);

...

signal signBit : std_logic;

begin
    signBit <= Din(15 downto 15);

The error given is:

Type of signBit is incompatible with type of Din.

Yes I get it, vectors don't play nice with std_logic, but this is 1-bit, clearly denoted by (15 downto 15)

Answer

Brian Drummond picture Brian Drummond · Mar 28, 2014 
Din(15 downto 15);

is a std_logic_vector, 1 bit long

Din(15);

is one element of a std_logic_vector, i.e. a std_logic.

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