Top "Vhdl" questions

Why does a 4 bit adder/subtractor implement its overflow detection by looking at BOTH of the last two carry-outs?

This is the diagram we were given for class: Why wouldn't you just use C4 in this image? If C4 …

vhdl boolean-logic circuit

Comparing a long std_logic_vector to zeros

In simulation this works perfect. Is this is the best way of checking for zeros for a synthesisable code. What …

vhdl

Using FOR loop in VHDL with a variable

Is there any possible way to create a for loop in the form: for i in 0 to some_var loop // …

loops for-loop while-loop vhdl synthesize

how to declare two dimensional arrays and their elements in VHDL

i need to declared the values that the counter is to take in a 2D array. Also, how do i …

vhdl

Conversion from numeric_std unsigned to std_logic_vector in vhdl

I have a question related to conversion from numeric_std to std_logic_vector. I am using moving average filter …

vhdl fpga xilinx hdl intel-fpga

VHDL - Adding two 8-bit vectors into a 9-bit vector

This is a pretty simple question, but I haven't been able to make this work yet, nor has any searching …

overflow vhdl

4-bit adder-subtractor logic

I have almost successfully implemented n-bit adder-subtractor. It works fine, except for one thing. Carry after an unsigned subtraction doesn't …

logic vhdl addition subtraction

VHDL difference between => and <=

I keep forgetting and its difficult to search for the answer in a textbook or the Internet.

syntax vhdl

VHDL driving signal from different processes

I have a little problem with following VHDL code: process (zbroji) begin if rising_edge(zbroji) then oduzima <= '0…

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VHDL: creating a very slow clock pulse based on a very fast clock

(I'd post this in EE but it seems there are far more VHDL questions here...) Background: I'm using the Xilinx …

vhdl clock fpga