Comparing a long std_logic_vector to zeros

vhdl
powernest picture powernest · Sep 25, 2013 · Viewed 27.8k times · Source

In simulation this works perfect. Is this is the best way of checking for zeros for a synthesisable code. What would be the resources generated?

signal vector_slv : std_logic_vector(2048 downto 0);
...
if (vector_slv = (vector_slv'range => '0')) then
  -- do something...

Is there any other optimal way to implement this solution considering h/w mapping (with optimal resource utilization).

I would be more interested in understanding the resources used.

Answer

Morten Zilmer picture Morten Zilmer · Sep 26, 2013

If the range is available, as in your example code, then the suggestion solution looks fine, and I would expect that synthesis tools are made to handle constructions like this.

If the range is not available, then compare with zero can be made like:

library ieee;
use ieee.numeric_std.all;
...
  if unsigned( {std_logic_vector expression of any length} ) = 0 then
    -- do something...

I would expect that synthesis tools handle this the same was as for compare with (vector_slv'range => '0').

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