VHDL difference between => and <=

syntax vhdl
Useless Intern picture Useless Intern · Nov 2, 2011 · Viewed 24.6k times · Source

I keep forgetting and its difficult to search for the answer in a textbook or the Internet.

Answer

Akron picture Akron · Nov 2, 2011

Well, <= is assignment.

signal <= A or B;

=> is syntax used for case statements like so: (Stolen from http://www.cs.umbc.edu/portal/help/VHDL/sequential.html)

case  my_val  is
  when 1 =>  // This is kind of like how the : operator is used for switch in many languages
    a:=b;
  when 3 =>
    c:=d;
    do_it;
  when others =>
    null; // do nothing
end case;

end case;

=> can also be used in array assignments

myVector <= (1=>'1', OTHERS=>'0');  -- assigns ('0','1','0','0') to "myVector"

Source: http://www.eda.org/comp.lang.vhdl/html3/gloss_example.html

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