For example, I have a vector which length is 10. How can I initialize it in hex. (The synthesize tool complains size mismatch as it thinks the hex value is a multiple of 4)
signal v : std_logic_vector (9 downto 0) := x"11A";
Many thanks! Nigong
x"11A"
is a "hexadecimal bit string literal". Prior to VHDL-2008, these had to be a multiple of 4 bits, hence the problem you're seeing. VHDL-2008 removed this restriction, so you can now write 10x"11A"
. I don't know how much tool support there is for 2008, though.