Error in VHDL (Xilinx): failed to link the design

user3527245 picture user3527245 · Apr 12, 2014 · Viewed 22.5k times · Source

why I get error in VHDL for this? Also, sometimes: cannot do process as a process failed previously?

Many thanks.

Answer

Purohit Gaurav picture Purohit Gaurav · Jul 11, 2016

Permanent solution 1: on win 10 Find the "installation directory \ Xilinx \ 14.x \ ISE_DS \ ISE \ gnu \ MinGW \ 5.0.0 \ nt \ libexec \ gcc \ mingw32 \ 3.4.2 \ collect2.exe" and delete it and re-run the emulator, the problem resolved! !

Just delete this or cut and paste somewhere as else, now re-run the code or test bench it will work.

Please accept the solution if find working

No need to update any minGW