padding out std_logic_vector with leading zeros

vhdl
James0 picture James0 · Mar 18, 2015 · Viewed 20.1k times · Source

ok, what I would like to do is assign a smaller std_vector to a large one, padding out the upper bits with zeros. But, I want something generic and simple that doesn't involve knowing the size of each first.

for instance if I have:

signal smaller_vec: std_logic_vector(15 downto 0);
signal larger_vec: std_logic_vector(31 downto 0);

I could do:

larger_vec <= X"0000" & smaller_vec;

But what if I don't know the size of the smaller vector. Is there a was of specifying that all upper bits are zero.

I know about the others clause, but that would get messy as I'd need a couple of lines:

larger_vec(smaller_vec'high downto 0) <= smaller_vec;
larger_vec(31 downto smaller_vec'length) <= (others => '0');

I thought I could use:

larger_vec <= "" & smaller_vec;

but this didn't work. any ideas?

Answer

Jim Lewis picture Jim Lewis · Mar 18, 2015

Have you tried:

larger_vec <= (31 downto smaller_vec'length => '0') & smaller_vec;

In the past I have had synthesis tool issues with code like that, so I have used:

constant ZERO : std_logic_vector(larger_vec'range) := (others => '0');
. . .
larger_vec <= ZERO(31 downto smaller_vec'length) & smaller_vec;

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