Top "Vhdl" questions

How to define clock input in Xilinx

Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course that is …

vhdl xilinx digital-logic

Can't infer register for ... at ... because it does not hold its value outside the clock edge

This must be the most common problem among people new to VHDL, but I don't see what I'm doing wrong …

vhdl fpga intel-fpga

Counter with push button switch design using VHDL and Xilinx

I'm very new to VHDL and XILINX ISE. I use the version 13.2 for Xilinx ISE. I want to design a …

vhdl fpga xilinx spartan

How to decode an unsigned integer into BCD use VHDL

As we can see that,in VHDL ,MOD and REM only can be simulated but can't be synthesized.So how …

integer vhdl bcd

Wait until <signal>=1 never true in VHDL simulation

Below is the code that I am running. My question is why doesn't the 3rd wait until trigger in modelsim? …

vhdl fpga modelsim

Time stamp in VHDL

is there any function in VHDL which is used to get current simulation time at which a process is running? …

vhdl fpga

short way to write VHDL priority encoder

Could you tell me if there is a better way to write a priority encoder in VHDL than just using …

if-statement vhdl encoder

VHDL alias syntax "<< ... >>"

I'd like to understand the syntax used in the line of code below where an alternate name is created using …

syntax alias vhdl

Pseudo Random Number Generator using LFSR in VHDL

I'm having a bit of trouble creating a prng using the lfsr method. Here is my code: library IEEE; use …

random numbers vhdl generator lfsr

wait statement must contain condition clause with UNTIL keyword

The following VHDL is to be used to test bench. I keep getting an error on the first wait statement …

vhdl intel-fpga quartus