How to decode an unsigned integer into BCD use VHDL

integer vhdl bcd
user1673133 picture user1673133 · Oct 18, 2012 · Viewed 11.8k times · Source

As we can see that,in VHDL ,MOD and REM only can be simulated but can't be synthesized.So how can we get the BCD from an unsigned integer? For example,the integer is 23,how can we get the BCD:0b0010 and 0b0011? Thanks.

Answer

Martin Thompson picture Martin Thompson · Oct 18, 2012

This has been covered elsewhere:

https://electronics.stackexchange.com/questions/22611/binary-to-bcd-converison

  • A lookup table is one option
  • A big case statement is another (Which will get turned into a lookup table)
  • Or an iterative method where you keep subtracting 10 until the remainder is < 10 - the count of subtractions is your tens digit, the remainder is your units digit.

Related questions

VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?

Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented (i.e if MAXVAL=5, then bitwidth= {wcalc "floor(logtwo($MAXVAL))+1"}). I'm aware I could do: SIGNAL myLogicVector : STD_LOGIC_VECTOR(2 …

Read More
When should I use std_logic_vector and when should I use other data types?

I'm new to VHDL and am having trouble figuring out which data types are appropriate to use where. If I understand correctly, for synthesis, all top level entity ports should be declared either std_logic_vector or std_logic and …

Read More
VHDL complement counter issues: converting std_logic to integer

Essentially, my question is: "can this not be done any easier?"; and what 'this' is, follows below (code too): I wanted to have a sort of a 'complement' counter function, implemented in VHDL, which would basically invert/complement/not the …

Read More