Can't infer register for ... at ... because it does not hold its value outside the clock edge

Harold Forrest picture Harold Forrest · May 13, 2011 · Viewed 11.9k times · Source

This must be the most common problem among people new to VHDL, but I don't see what I'm doing wrong here! This seems to conform to all of the idioms that I've seen on proper state machine design. I'm compiling in Altera Quartus 9.2, for what it's worth. The actual error is:

"Can't infer register for "spiclk_out" at [file] [line] because it does not hold its value outside the clock edge"

ENTITY spi_state_machine IS
    PORT(
            spiclk_internal : IN STD_LOGIC;
            reset : IN STD_LOGIC;
            spiclk_out : BUFFER STD_LOGIC
    );
END spi_state_machine;

PROCESS(spiclk_internal, reset)
BEGIN
    IF reset = '1' THEN
        spiclk_out <= '0';
    END IF;

    IF spiclk_internal = '1' AND spiclk_internal'EVENT THEN --error here
        spiclk_out <= NOT spiclk_out;
    END IF;
END PROCESS;

Thanks for your time.

Answer

Tomi Junnila picture Tomi Junnila · May 13, 2011

As written, the process would cause spiclk_out to toggle on spiclk_internal edges even when reset is active, which is not how flip-flops with asynchronous resets should behave.

What you probably want is

SPICLK: process(spiclk_internal, reset)
    if reset = '1' then
        spiclk_out <= '0';
    elsif spiclk_internal'event and spiclk_internal='1' then
        spiclk_out <= not spiclk_out;
    end if;
end process SPICLK;