Top "Vhdl" questions

VGA Text display using VHDL on DE1

I am doing animation of algorithms using VHDL on Altera DE1. In this project, I have to display text to …

vhdl fpga vga

Creating a frequency divider in VHDL

MAJOR EDIT: Problem was solved after reading Will Dean's comment. The original question is below the revised code: -- REVISED …

vhdl intel-fpga

Is there a way to print the values of a signal to a file from a modelsim simulation?

I need to get the values of several signals to check them against the simulation (the simulation is in Matlab). …

vhdl modelsim

Where can I find a definitive list of the ModelSim error codes?

I am running some VHDL through ModelSim. Each error and warning has its own error code (like this: (vcom-1292) Slice …

vhdl fpga modelsim

Function with don't-care inputs

How can I implement a VHDL function which has "don't care" inputs and have the "don't cares" be directly represented? …

vhdl truthtable

Why is rising edge preferred over falling edge

Flip-Flops(,Registers ...) are usually triggered by a rising or falling edge. But mostly in code you see an if-clause which …

hardware vhdl synthesis

ps/2 keyboard interface VHDL

Alright so I'm trying to implement a keyboard controller for use with an altera DE2 FPGA board, and am having …

keyboard vhdl fpga intel-fpga ps2

simple axi lite slave application

I am using Vivado 2015.3 and a Zybo board and I am trying to implement a very simple AXI lite IP …

vhdl vivado zynq

FIFO with 2 clocks in VHDL

I have a problem with a vhdl assignment. I need to create a FIFO buffer between a bus of 500MHz …

vhdl fifo clock-synchronization clock

VHDL: signals and ports on which side of the "arrow" =>

very basic question: How do I know where the port/signal/value should be placed on which side of the …

vhdl fpga xilinx