Top "Vivado" questions

how to solve 4 bit full adder verilog

I am supposed to create 4 bit full adder verilog code in vivado.But when I try to test in the …

xilinx vivado

Error "procedural assignment to a non-register result is not permitted"

I'm getting the error [Synth 8-2576] procedural assignment to a non-register result is not permitted ["lpm_mult.v":29] What am …

verilog vivado

Type conversion in VHDL: real to integer - Is the rounding mode specified?

While debugging the handling of user defined physical types in Vivado (read more), I found a different behavior for type …

type-conversion vhdl xilinx xilinx-ise vivado

How to initialize contents of inferred Block RAM (BRAM) in Verilog

I am having trouble initializing the contents of an inferred ram in Verilog. The code for the ram is as …

verilog fpga xilinx vivado

Use of Xil_Out32 in Xilinx SDK

In Vivado I succesfully made a simple blockdiagram to control the LEDs of my Zybo board. I can observe that …

fpga xilinx zynq vivado

simple axi lite slave application

I am using Vivado 2015.3 and a Zybo board and I am trying to implement a very simple AXI lite IP …

vhdl vivado zynq