Top "Xilinx-ise" questions

Xilinx ISE is the toolchain package for programming Xilinx FPGAs in VHDL and Verilog.

Verilog: How to delay an input signal by one clock cycle?

I would like to delay an input signal by one complete clock cycle.I have the code below which basically …

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verilog clock system-verilog xilinx-ise
Type conversion in VHDL: real to integer - Is the rounding mode specified?

While debugging the handling of user defined physical types in Vivado (read more), I found a different behavior for type …

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type-conversion vhdl xilinx xilinx-ise vivado
how do i initialize a std_logic_vector in VHDL?

i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below: architecture Behavioral of test …

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vhdl hdl xilinx-ise
Connecting a STD_LOGIC to a one bit STD_LOGIC_VECTOR

I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard. The problem is that it …

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