Top "Synthesis" questions

Convert Mat to Array/Vector in OpenCV

I am novice in OpenCV. Recently, I have troubles finding OpenCV functions to convert from Mat to Array. I researched …

c++ arrays opencv vector synthesis

Sound generation / synthesis with python?

Is it possible to get python to generate a simple sound like a sine wave? Is there a module available …

python python-3.x python-2.7 audio synthesis

@property and @synthesize in objective-c

While I was playing and figure out how things work in https://github.com/enormego/EGOTableViewPullRefresh I found mysterious of @…

objective-c properties synthesis

VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?

Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented (…

integer logic width vhdl synthesis

I want to learn audio programming

At my high school we can take a class where we basically learn about a subject on our own for …

audio signal-processing synthesis

Seven Segment Multiplexing on Basys2

this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four …

verilog fpga hdl synthesis multiplexing

How to NOT use while() loops in verilog (for synthesis)?

I've gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats …

loops verilog synthesis

Sound synthesis with C#

Is there some possibility to generate sounds in C#? I mean not just beep or open and play wave-file. I …

c# .net audio signals synthesis

Is $readmem synthesizable in Verilog?

I am trying to implement a microcontroller on an FPGA, and I need to give it a ROM for its …

verilog synthesis

VHDL: The following files are missing: .stx, .ncd, .xrpt

Before I even start with synthesis(as soon as I press "Save"), I get this warnings: WARNING:ProjectMgmt - File …

file save warnings vhdl synthesis