FIFO with 2 clocks in VHDL

vhdl fifo clock-synchronization clock
Jordan Lee Gauci picture Jordan Lee Gauci · May 2, 2013 · Viewed 8.4k times · Source

I have a problem with a vhdl assignment. I need to create a FIFO buffer between a bus of 500MHz and another bus of 30MHz.

I have designed a basic FIFO buffer with

inputs: Data_in, Write_EN, CLK_500, Read_EN, CLK_30, FlushFIFO.

outputs: Data_out, FULL, EMPTY.

This buffer was designed using a 2D array:

type fifo_arr is array (0 to 63) of std_logic_vector(39 downto 0);
signal FIFO : fifo_arr := (others => (others => '0'));

The problem is the following: How should I write the processes and maintain a pointer between them for synchronization? With the method that I have tried, the code will not synthesize (ERROR:XST:827 Signal ptr cannot be synthesized)

Any ideas?

thanks and regards

Answer

Martin Thompson picture Martin Thompson · May 2, 2013

It might be an idea to show us the code that it actually complained about!

FIFOs across clock domains are tricky, not to be attempted lightly...

Having said that - as it looks like a homework assignment, a good read can be found here:

http://eda.ee.nctu.edu.tw/jdhuang/courses/ipcd04/paper/alfke_final.pdf

(one of the authors is the late, great, Peter Alfke - he designed the first FIFO chip, in 1969, and is widely regarded as a, or even the, FIFO-guru)

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