How to make the 2-complement of a number without using adder

vhdl verilog fpga twos-complement
HBv6 picture HBv6 · Jan 26, 2013 · Viewed 14.4k times · Source

In two-complement to invert the sign of a number you usually just negate every bit and add 1. For example:

011 (3)
100 + 1 = 101 (-3)

In VHDL is:

a <= std_logic_vector(unsigned(not(a)) + 1);

In this way the synthesizer uses an N-bit adder.

Is there another more efficient solution without using the adder?

Answer

Tim picture Tim · Jan 26, 2013

I would guess there's not an easier way to do it, but the adder is probably not as bad as you think it is.

If you are trying to say invert a 32-bit number, the synthesis tool might start with a 32-bit adder structure. However then upon seeing that the B input is always tied to 1, it can 'hollow out' a lot of the structure due to the unused gates (AND gates with one pin tied to ground, OR gates with one pin tied to logic 1, etc).

So what you're left with I'd imagine would be a reasonably efficient blob of logic which just increments an input number.

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