Creating a VHDL backend for LLVM?

llvm vhdl
aneccodeal picture aneccodeal · Sep 8, 2010 · Viewed 9.1k times · Source

LLVM is very modular and allows you to fairly easily define new backends. However most of the documentation/tutorials on creating an LLVM backend focus on adding a new processor instruction set and registers. I'm wondering what it would take to create a VHDL backend for LLVM? Are there examples of using LLVM to go from one higher level language to another?

Just to clarify: are there examples of translating LLVM IR to a higher level language instead of to an assembly language? For example: you could read in C with Clang, use LLVM to do some optimization and then write out code in another language like Java or maybe Fortran.

Answer

JCLL picture JCLL · Feb 1, 2011

Yes !

There are many LLVM back-end targeting VHDL/Verilog around :

And I know there are many others...

The interesting thing about such low-level representations as LLVM or GIMPLE (also called RTL by the the way) is that they expose static-single assignments (SSA) forms : this can be translated to hardware quite directly, as SSA can be seen as a tree of multiplexers...

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