Popular "verilog" questions | Page 17

I am attempting to program an addition and subtraction program in Verilog. Problem is Implementation and testing in Verilog of …

verilog digital-logic digital-design

I have written verilog code for fifo using fillcount to check as the means for checking if it is full …

verilog fifo vlsi

I'm new to Verilog. Can someone suggest a learning resource, book, video, blog or anything that they had a good …

microcontroller verilog fpga

I am trying to display a real number during the simulation of my verilog code in modelsim. But I only …

verilog modelsim

I have written something small in verilog: `define LW 6'b100011 `define SW 6'b101011 parameter [3:0] i_fetch = 4'b0001, decode_rr = 4'b0010, …

syntax global verilog modelsim

Let's say module_a has register_a in it, which needs to be linked to module_b. Should register_a …

verilog hdl

I looked through internet and couldn't find a clear and concise answer to my question. I want to know what'll …

conflict verilog drive signal-strength

Is there way to get system time in VCS/UVM ? I am looking for something similar to Perl's localtime(time). …

verilog system-verilog uvm synopsys-vcs

I want to build a T-flip flop in Verilog. So far I have written the following code, but I wish …

verilog flip-flop

What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example: logic [15:0] down_vect; …

verilog system-verilog

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