Modules in Verilog: output reg vs assign reg to wire output

Question

Let's say module_a has register_a in it, which needs to be linked to module_b. Should register_a be declared separately and assigned to an output of module_a:

reg register_a;
assign output_a = register_a;

or should we just declare output_a with a reg inline in the module declaration and use that in the code?

Answer 1

I think you are asking about the difference between the following:

module my_dff (output reg q, input clk, d); //None Blocking style
  always @(posedge clk) begin
    q <= d;
  end
endmodule

vs

module my_dff (output q, input clk, d);
  reg reg_q;
  assign q = reg_q; // Blocking style
  always @(posedge clk) begin
    reg_q <= d;
  end
endmodule

Between the two, there is no functional difference. It is mostly a coding preference. There are a hand full of simulators that do not enforce directional of inputs and outputs, so if a there are accidentally two modules driving the same net, those simulators an X can propagate X to the register with output reg. This is a rare scenario, most simulators (especially the mainstream ones) don't have this issue.

I personally prefer output reg mainly because it is fewer lines of code.

Regardless of how the output type is declared, when you instantiate the module, the output needs to be connected to a net-type (eg wire), not a reg. Inputs can be either type.

module fifo(output out, input clk, in);
  wire q0;
  reg q1;
  my_dff dff0 ( q0, clk, in );
  always @(posedge clk) begin
    q1 <= q0;
  end
  my_dff dff1 ( out, clk, q1 );
endmodule