What is the difference between == and === in Verilog?

verilog hdl
user478571 picture user478571 · May 8, 2011 · Viewed 90.1k times · Source

What is the difference between:

if (dataoutput[7:0] == 8'bx) begin

and

if (dataoutput[7:0] === 8'bx) begin

After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)

Answer

toolic picture toolic · May 8, 2011

Some data types in Verilog, such as reg, are 4-state. This means that each bit can be one of 4 values: 0,1,x,z.

With the "case equality" operator, ===, x's are compared, and the result is 1.

With ==, the result of the comparison is not 0, as you stated; rather, the result is x, according to the IEEE Std (1800-2009), section 11.4.5 "Equality operators":

For the logical equality and logical inequality operators (== and !=), if, due to unknown or high-impedance bits in the operands, the relation is ambiguous, then the result shall be a 1-bit unknown value (x).

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