Conditional instantiation of verilog module

Question

Is it possible to instantiate a module conditionally in verliog ?

example :

if (en==1)  
  then module1 instantiation  
else  
  module2 instantiation  

Answer 1

From IEEE Std 1364-2001 :

12.1.3.3 generate-conditional A generate-conditional is an if-else-if generate construct that permits modules, user defined primitives, Verilog gate primitives, continuous assignments, initial blocks and always blocks to be conditionally instantiated into another module based on an expression that is deterministic at the time the design is elaborated.

example given in LRM :

module multiplier(a,b,product);
parameter a_width = 8, b_width = 8;
localparam product_width = a_width+b_width; // can not be modified
// directly with the defparam statement
// or the module instance statement #
input [a_width-1:0] a;
input [b_width-1:0] b;
output [product_width-1:0] product;

generate
    if((a_width < 8) || (b_width < 8))
        CLA_multiplier #(a_width,b_width) u1(a, b, product);
        // instantiate a CLA multiplier
    else
        WALLACE_multiplier #(a_width,b_width) u1(a, b, product);
        // instantiate a Wallace-tree multiplier
endgenerate
// The generated instance name is u1

endmodule