If statement and assigning wires in Verilog

Question

I am trying to figure out the basics of assigning wires based on combinational logic.

I have:

wire val;
wire x;
wire a;
wire b;

always @*
begin

if(val == 00)
 //I want to assign x = a
if(val == 01)
 //I want to assign x = b

end

where a and b are wires with values - and x is a wire going into a register.

If you can point me in the right direction to what I need to change, it would be much appreciated.

Answer 1

wires can only be assigned by assign statements, which can not be used with if statements. If you change x to reg type, then you will be able to assign it in an always block.

This will synthesize exactly the same, a common misconception is that a reg type variable implies a register, but it just changes the way the value is assigned.

Alternatively, you can use an assign statement with ternary operator ?:, if you want it to remain as a wire type:

assign x = (val==0) ?   a : 
           (val==1) ?   b : 
                      'bx ;