Top "Verilog" questions

VIM highlight matching begin/end

I'm trying to find a plugin that will highlight the matching begin/end statements with Verilog. VIM has it working …

vim syntax syntax-highlighting verilog vim-syntax-highlighting

inout with reg type in verilog

I have used inout with c, but for c to be on the LHS of procedural assignment, it needs to …

verilog inout

Program to create a Verilog block diagram

I want to create a program to parse Verilog and display a block diagram. Can someone help me regarding what …

algorithm verilog register-transfer-level

How to restart a Verilog simulation in Modelsim

I'm trying to debug a Verilog module. I find it tedious to have to stop a simulation, modify code, and …

debugging module verilog modelsim

Behavioral verilog bcd up down counter with enable and reset

I recently need to make a BCD up down counter with enable and reset. I have three always blocks but …

counter verilog behavior bcd seven-segment-display

Warning: (vsim-7) Failed to open readmem file "mem_content_01.dat" in read mode

I am trying to run a test simulation in ModelSim and am getting the error in the title. I have …

verilog system-verilog modelsim

Data memory unit

I started Verilog a few weeks ago and now I'm implementing MIPS pipelining on an FPGA board and I'm on …

verilog mips32

SystemVerilog support of icarus (iverilog compiler)

I am using iverilog on a Mac, and I have problem compiling some codes that include always_ff and always_…

verilog hardware system-verilog iverilog icarus

Finding Absolute Value In Verilog Data Designated by System C/Xilinx X

I have been trying to find the Absolute value of an integer which is designated to Verilog core using Xilinx …

c verilog fpga xilinx microblaze

Doxygen alternative for Verilog, SystemVerilog?

Project "doxverilog" is not supported more, author's site is not responding. Project http://intelligentdv.com/downloads/index.html#doxygentools works …

verilog doxygen fpga system-verilog asic