Top "Asic" questions

Tool for drawing timing diagrams

Recently I am working with a hardware design group developing an ASIC. And I am drawing a lot of timing …

hardware verilog asic timing-diagram

Case statement in verilog

I came across priority encoder design and found out a new way to do it using a case statement. The …

verilog asic

Compilation error: A net is not a legal lvalue in this context

I am a newbie to Verilog and had a problem while defining a if-else loop. The error message is A …

verilog asic digital-design

Doxygen alternative for Verilog, SystemVerilog?

Project "doxverilog" is not supported more, author's site is not responding. Project http://intelligentdv.com/downloads/index.html#doxygentools works …

verilog doxygen fpga system-verilog asic