Top "Verilog" questions

How do I access an array element using a variable as index?

I'm trying to access an element from an array using an input as index and I keep getting this error: …

arrays reference verilog iverilog

How to generate schematic file from verilog source in Xilinx

What I'm doing I started playing around with Xilinx ISE Design Suite and wrote simple Arithmetical Logic Units in verilog. …

verilog xilinx

Printing packed structs in System Verilog

I have a packed struct defined as shown below typedef struct packed { logic bit1; logic [7:0] byte1; } MyPackedStruct; MyPackedStruct myPackedStruct; Is …

printing struct verilog system-verilog packed

How to write a linter?

In my day job I, and others on my team write a lot of hardware models in Verilog-AMS, a language …

coding-style verilog syntax-checking

Illegal operand for constant expression

I'm trying to build a task, which must delve into some hierarchy, that can concisely compare different pins on a …

verilog cadence

Verilog linting tools?

What are some good linting tools for verilog? I'd prefer one that can be configured to either handle or ignore …

verilog lint typechecking hdl

How can I separate long statements into lines in Verilog

For example, I have a single long statement: $display("input_data: %x, output_data: %x, result: %x", input_data, output_…

verilog

What is the point of a "plain" begin-end block?

I'm reading some third party Verilog, and found this: function [31:0] factorial; input [3:0] operand; reg [3:0] index; begin factorial = operand ? 1 : 0; for(index = 2; …

verilog system-verilog

Design 32 bit arithmetic logic unit (ALU)

I write this coder for an ALU. This ALU controlled with ctrl signals and do some works like add, subtract, …

verilog alu

Verilog case statement

Could we have any syntax where case statement is scalable? Let me explain with an example: Mux If there were …

verilog case-statement