Printing packed structs in System Verilog

printing struct verilog system-verilog packed
Vissu picture Vissu · Jul 2, 2014 · Viewed 11.7k times · Source

I have a packed struct defined as shown below

typedef struct packed {
    logic bit1;
    logic [7:0] byte1;
} MyPackedStruct;

MyPackedStruct myPackedStruct;

Is there any SV built in function that I could use to print the structures similar to above but having many more fields, without having to write my own method to print each of the fields using a

$display(...,myPackedStruct.field_name)?

Answer

dwikle picture dwikle · Jul 2, 2014

You can use the %p formatting element.

$display("%p", myPackedStruct);

Output from Modelsim:

 # '{bit1:x, byte1:x}

See section 21.2.1.7 Assignment pattern format in the IEEE 1800-2012 SystemVerilog language spec.

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