Top "Verilog" questions

How to use verilog $deposit with indexes

How can $deposit be used when the path includes the index from the generate loop. When I try: for(int …

verilog system-verilog register-transfer-level

Implementing one-bit flags in a 32Bit ALU using Verilog

I am working on an assignment and am a little lost and don't really know how to get started. I …

verilog digital-logic alu iverilog status-register

Frequency divisor in verilog

i need a frequency divider in verilog, and i made the code below. It works, but i want to know …

verilog clock frequency circuit digital-logic

Shifting 2D array Verilog

I dont know what doesnt work on the following code, but it wont synthesize: reg [7:0] FIFO [0:8]; always@(posedge clk) begin …

arrays verilog concat shift fifo

Calculations with Real Numbers, Verilog HDL

I noticed that Verilog rounds my real number results into integer results. For example when I look at simulator, it …

numbers verilog hdl real-datatype

Always vs forever in Verilog HDL

What are the difference between the always keyword (not the always @ block) and forever keyword in Verilog HDL? always #1 a=!…

verilog hdl icarus

Verilog multiple drivers

I'm trying to make BCD Counter using Verilog that will be connected to 7-segment decoder.After I synthesize it, the …

verilog xilinx system-verilog bcd

How to design a 64 x 64 bit array multiplier in Verilog?

I know how to design a 4x4 array multiplier , but if I follow the same logic , the coding becomes tedious. 4 …

verilog multiplication

Width independent functions

Is it possible to write a function that can detect the input data width automatically? For example, consider the parity …

verilog system-verilog

Verilog error: not a valid l-value

I'm trying to test if a wire(s) is on or not to signify if there is an error/overflow …

verilog alu