Top "Register-transfer-level" questions

$display vs $strobe vs $monitor in verilog?

What is the difference between $display vs $strobe vs $monitor in verilog? When in the event queue does each apply, …

verilog vlsi register-transfer-level

How to define and initialize a vector containing only ones in Verilog?

If I want to declare a 128 bit vector of all ones, which one of these methods is always correct? wire [127:0] …

verilog system-verilog register-transfer-level

How to use clock gating in RTL?

I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place &…

verilog system-verilog register-transfer-level vlsi

Difference between scoreboard and checker

I have started developing a testbench for my RTL DUT. With all the components of the testbench, I want to …

verilog verification system-verilog register-transfer-level uvm

How to use verilog $deposit with indexes

How can $deposit be used when the path includes the index from the generate loop. When I try: for(int …

verilog system-verilog register-transfer-level

Program to create a Verilog block diagram

I want to create a program to parse Verilog and display a block diagram. Can someone help me regarding what …

algorithm verilog register-transfer-level

System Verilog always_latch vs. always_ff

Just started learning System Verilog. I am confused about the usage of statements always_ff and always_latch. The former …

system-verilog vlsi register-transfer-level