Difference between scoreboard and checker

verilog verification system-verilog register-transfer-level uvm
Suhas picture Suhas · Nov 21, 2013 · Viewed 13.4k times · Source

I have started developing a testbench for my RTL DUT. With all the components of the testbench, I want to implement self-checking mechanism for the verification of the functionality of the DUT.

Hence, i need to develop scoreboard component. But here, i get even the checker component concept.

What is the difference between Scoreboard and Checker components?

And also its application?

When is it needed to use either scoreboard or checker or both ?

Thanks.

Answer

dave_59 picture dave_59 · Nov 21, 2013

In general terminology, checkers and scoreboards are used interchangeably and both compare actual results from the DUT to expected results. However a checker usually is specific to an independent piece of functionality that you want to verify, whereas a scoreboard may be a collection of one or more checkers for an interface or the entire DUT. A scoreboard may also have responsibility for determining when "The Test" is done.

I think the origination of the term scoreboard used in verification came from the database used to store expected results and the test was considered done when all entries in the the database where checked off as completed, or the database was empty because you had removed each entry as the actual results came in from the DUT. The UVM uses uvm_scoreboard to represent the component in the testbench that contains this database.

SystemVerilog 1800-2009 reserved the keyword checker as an encapsulation block for building verification libraries of assertions along with modeling code for formal verification. But I still think of a checker as any encapsulation of re-usable code for checking expected against actual results.

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