Top "Uvm" questions

Difference between scoreboard and checker

I have started developing a testbench for my RTL DUT. With all the components of the testbench, I want to …

verilog verification system-verilog register-transfer-level uvm

how to use assertoff from test to disable assertion in side uvm object

I am looking for way to disable assert in side uvm component for certain test. Below simple code represent my …

system-verilog uvm system-verilog-assertions

How can I use foreach and fork together to do something in parallel?

This question is not UVM specific but the example that I am working on is UVM related. I have an …

foreach fork system-verilog uvm

How to print the whole queue/array with UVM utility functions?

For UVM objects using `uvm_field_queue_int utility macro, UVM does not print out the whole queue when calling …

printing queue system-verilog uvm

Difference Between the uvm_analysis ports

Can you please help to understand the functionality and clear difference between: uvm_analysis_export uvm_analysis_port uvm_analysis_…

uvm

UVM: illegal combination of driver and procedural assignment warning

I have a UVM testbench for a small block in my chip. In this there is an agent with a …

system-verilog uvm

Get system time in VCS

Is there way to get system time in VCS/UVM ? I am looking for something similar to Perl's localtime(time). …

verilog system-verilog uvm synopsys-vcs