Difference Between the uvm_analysis ports

uvm
haykp picture haykp · Mar 1, 2016 · Viewed 8.1k times · Source

Can you please help to understand the functionality and clear difference between:

  1. uvm_analysis_export
  2. uvm_analysis_port
  3. uvm_analysis_imp

I have searched in internet, there are some explanations, like those:

But still I feel that need more explanation. Can someone help please.

Answer

Ashley Winn picture Ashley Winn · Mar 1, 2016

uvm_analysis_port's are the publisher, they broadcast transactions

uvm_analysis_imp's are the subscriber, they receive transactions and call a function named 'write' in the class in which they are defined.

uvm_analysis_export's can be more confusing, they are used to expose 'imp' ports at higher level of the hierarchy. For example if you have an agent which contains a component with an analysis_imp and you want to make that 'imp' available at the agent's interface level. In this situation you declare and instantiate the analysis_export in the agent class, then in the connect_phase connect the agent's analysis_export to your internal component's analysis_imp.

Its worth noting, exports are for the subscribing side, but on the publishing side regular uvm_analysis_port's can be used in the same way. So agent's can instantiate analysis_ports and connect them to an internal component's analysis_port.

This is good because it allows you to avoid reaching down into the hierarchy when you are connecting components (which makes maintenance easier):

bad: 

bus_agent.internal_monitor.packet_port.connect(checker.ref_model.packet_imp)

good:

bus_agent.packet_port.connect(checker.packet_export)

Its also good to become familiar with the macro uvm_analysis_imp_decl(). It allows you to use more than one analysis_imp in a component.

Related questions

Difference between scoreboard and checker

I have started developing a testbench for my RTL DUT. With all the components of the testbench, I want to implement self-checking mechanism for the verification of the functionality of the DUT. Hence, i need to develop scoreboard component. But …

Read More
how to use assertoff from test to disable assertion in side uvm object

I am looking for way to disable assert in side uvm component for certain test. Below simple code represent my env, with comment for requirement. I thought I can use $assertoff. I can modify uvm component if required additional instrumentation …

Read More
How can I use foreach and fork together to do something in parallel?

This question is not UVM specific but the example that I am working on is UVM related. I have an array of agents in my UVM environment and I would like to launch a sequence on all of them in …

Read More