How to define and initialize a vector containing only ones in Verilog?

verilog system-verilog register-transfer-level
Veridian picture Veridian · Oct 1, 2013 · Viewed 22.9k times · Source

If I want to declare a 128 bit vector of all ones, which one of these methods is always correct?

wire [127:0] mywire;

assign mywire = 128'b1;
assign mywire = {128{1'b1}};
assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

Answer

toolic picture toolic · Oct 1, 2013

As a quick simulation would prove, assign mywire = 128'b1; does not assign all bits of mywire to 1. Only bit 0 is assigned 1.

Both of the following always assign all 128 bits to 1:

assign mywire = {128{1'b1}};
assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

One advantage of the 1st line is that it is more easily scalable to widths greater than and less than 128.

With SystemVerilog, the following syntax also always assigns all 128 bits to 1:

assign mywire = '1;

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